Dual-mode convolutional/SOVA based turbo code decoder VLSI design for wireless communication systems

A prototype design of a dual-mode convolutional/turbo code decoder for 3/sup rd/ generation wireless communication systems is proposed. By merging some similar modules exist in the convolutional code and turbo code decoder, we build one dual-mode decoder with these two functions. Besides, in order to conform to the CDMA2000 standard, the architecture can also perform as a reconfigurable Viterbi decoder. It means that our decoder meets the multi code rate and multi generator polynomial convolutional code specification. The final prototyping chip is presented with Avant! 0.35 /spl mu/m standard cell library.