A low-power 6-b integrating-pipeline hybrid analog-to-digital converter [Bluetooth transceiver applications]

This paper presents a novel low-power 6 bit ADC architecture for Bluetooth transceivers. It utilizes sequentially staged 3-bit integrating converters with interleaved sample and hold circuits. The characteristics of this architecture as well as areas that could lead to even more efficient devices are discussed. The device consumes 5.88 mA of current, 14.7 mW of power at a sampling rate of 50 MSamples/s, has an INL and DNL of 0.3 and 0.5 LSB, SNR of 36.6 dB, THD of 43.75 dB, and SFDR of 47.98 dB. Our architecture represents a 3.8 times improvement in power consumption, or a sampling rate with higher precision, compared to previously reported 6 bit implementations. An experimental prototype was simulated in 0.25 /spl mu/m CMOS, with a supply voltage of 2.5 V.