A hierarchical partitioning algorithm for VLSI designs

A hierarchical partitioning algorithm (HPA) partitions a circuit to several physical blocks while maintaining the logical hierarchy of the circuit. It uses a cost function which combines the net-cut, path-weight, and area of each module. A dynamic programming-based approach is utilized to find the minimal cost for different numbers of partitions. The area constraint helps the HPA to obtain area-balanced partitioning results in a shorter CPU time. The program has been tested on several industrial circuits. Experimental results are presented.