3-D placement considering vertical interconnects

3D integration is going to play an important role in the future. Increasing complexity and increasing impact of interconnects to integrated circuit (IC) performance makes 3D more and more attractive. EDA tools for 3D design hardly exist. We propose a new 3D standard-cell placer based on quadratic programming. It ensures a reduction of the total wirelength and can deal with standard cells and vertical interconnects simultaneously. The final result is a legalized, design rule compliant and discrete 3D placement.