Independent clocks for peripheral modules in system-on-chip design

A robust solution for enabling the use of independent clocks for peripheral modules in system-on-chip design is proposed. By combining a standard synchronous on-chip bus architecture with GALS methodology, the advantage of a high-bandwidth low-latency system bus and independent clock domains for peripheral modules is achieved. The peripheral modules are still allowed to have continuous clocks and operate as in a standard synchronous environment. The solution is tested in an existing AMBA based simulation testbed, and correct behavioral functionality is confirmed.