Hierarchical DSP architectural synthesis and scheduling solution for "IRIS"

Increasingly, DSP design flows need to cope with a hierarchy involving complex components rather than simple blocks such as multipliers. The paper outlines some of the challenges of such a design approach using a wave digital filter example. The paper outlines how an "in-house" architectural synthesis tool, IRIS, has been modified to synthesize such structures. An extended MARS (Minnesota architecture synthesis) scheduling algorithm for hierarchical scheduling is also proposed for reducing the area of the synthesized circuit.