Architectures and design considerations of CMOS charge pumps for phase-locked loops

A comprehensive review of the architectures of CMOS charge pumps for phase-locked loops and an in-depth comparison of their characteristics, such as speed, minimum supply voltage, mismatch-induced errors, charge injection and clock feed-through induced error's, and noise rejection, are presented. These charge pumps arc implemented in a 0.13/spl mu/ CMOS technology and analyzed using Spectre. Simulation results are presented.