Improving the interleaved signature instruction stream technique

Control flow monitoring using a watchdog processor is a well-known technique to increase the dependability of a microprocessor system. Most approaches embed reference signatures for the watchdog processor into the processor instruction stream creating noticeable memory and performance overheads. A novel embedding signatures technique called interleaved signatures instruction stream has been recently presented. Targeted to processors included into field-programmable devices, its main goal is to reduce the performance penalty produced by the watchdog processor in previous proposals. The work presented here is an improvement of this technique and offers a solution to the memory overhead without sacrificing performance, thus yielding a better overall architecture. We have called this improved technique OSIRIS: another interleaved signature instruction stream.