Stacked chip scale packages: manufacturing issues, reliability results, and cost analysis

System requirements for high density packaging have driven the development of chip scale package (CSP) technology. Continuing pressure for improved performance and reduced cost is dictating even greater improvements in functional density. A prime example of this can be found in the escalating requirements for DRAM and other memory modules. Functional integration within the silicon and bare chip stacking are two approaches to these challenges, but they present problems related to cost, time-to-market, testing, and business logistics. Stacking of tested CSPs - rather than bare chips-can address each of the issues because of increased design flexibility, the ability to extend the life of existing products, an established manufacturing infrastructure, and elimination of the technical and business challenges associated with procuring and testing bare die. With proper design, CSP stacking is a straightforward extension of standard packaging and surface mount processes. This paper reviews the manufacturing flow for one such stacked CSP technology, the /spl mu/Z/sup TM/-Ball Stack package. For any such high volume process, reliability is a critical issue, and reliability results for stacked CSP structures are presented. Most often, cost is the ultimate deciding factor in the selection of manufacturing technology, and a detailed cost analysis of package stacking versus die stacking is also presented. Much of the benefit can be found in the impact of the packaging technology on other parts of the supply chain, so the scope of the cost analysis extends beyond just the cost of the package. This approach can be used for analysis of any CSP stacking technology.