A new wafer level package for improved electrical and reliability performance

Wafer level packages (WLPs) have demonstrated a very clear size and cost advantage vs. traditional wirebond technologies, especially for small components that have a high number of dice and I/O per wafer. The Kulicke & Soffa Flip Chip Division (FCD) introduced it's first WLP in 1998. This initial WLP utilized a bump on nitride structure (BON) which had good reliability but also high input capacitance. A new WLP has been developed by FCD. This new WLP has a solder bump on polymer (BOP) dielectric structure. A major driver for pursuing a BOP structure was to achieve minimal input capacitance for high speed applications. During development, a new polymer dielectric material was carefully selected based on reliability tests and manufacturability. Thermal Cycling (TC) test showed 30% better TC performance vs. the BON structure. The new WLP also passed 168 hours of autoclave and JEDEC Level 1 Preconditioning testing. In this paper, the advantages of this new WLP will be discussed in detail. In addition, reliability test results will be presented.