Competitive 5V-thin and 12V-thick dual gate technology isolated drain LDMOS devices

Integrated power FETs in dc-dc converters should have good CHC rating so the on-resistance of the FETs does not walk outside its guaranteed limits over its intended lifetime thereby increasing the power losses. Planar devices are somewhat limited by CHC physics of gate oxide and drain engineering and not BVdss. The device presented at ISPSD02 was re-engineered in the quest for an isolated FET with BVdss greater than 22V, and meeting the system requirements for a 16V product rating. Data for thin (150 /spl Aring/) and thick gate versions (425 /spl Aring/) of the same device style in a 0.72/spl mu/m technology is presented along with 2D simulation results. The thick gate version shows a slight improvement but not enough to meet the above requirements. Much improved data for a re-engineered device is presented.