Doping accuracy requirements of USJ processes for advanced sub-100 nm CMOS devices

The gate length in advanced logic devices is being scaled increasingly aggressively to achieve speed requirements. It is therefore essential that device performance at short gate lengths (Vt roll-off, sub-threshold leakage) have a tight distribution, to avoid a spread of device performance or poor yield. The short channel behaviour of sub-100 nm devices is becoming increasingly sensitive to the source-drain extension region, and the accuracy of processing tools used to dope this region therefore have a direct effect on the device variability. However it has not been determined before which process parameters in the doping process have the largest effect on device performance, and this understanding is vital in setting the accuracy specification of implant and annealing tools for volume production. In this paper we review device data obtained in skew test experiments, aimed at establishing the sensitivity of device performance to different USJ (Ultra Shallow Junction) processing parameters. Advanced CMOS LOGIC devices were processed by ion implantation and rapid thermal annealing, using a matrix of implant and anneal parameters. NMOS and PMOS devices with gate lengths below 100 nm were processed using a 90 nm USJ module process, incorporating sub-keV implantation and spike annealing. A number of process parameters were then varied, including: implant energy, implanted dose, energy contamination level, spike anneal peak temperature and anneal ramp-up cool-down rates. The implant and anneals were done a Quantum Leap implanter and a Radiance RTP respectively. Various features including junction depth (X/sub j/), sheet resistance and other device parameters were examined in order to quantify the sensitivity of the devices to the implant and anneal parameters. From these results the required accuracy, uniformity and repeatability specifications were determined, for the implant and annealing tools to be used for production of sub-100 nm node CMOS devices.