New single-poly EEPROM with cell size down to 8F/sup 2/ for high density embedded nonvolatile memory applications

A novel EEPROM memory cell with new program and erase operations fabricated by standard CMOS logic process is presented. The cell which consists of two N-Type MOSFET transistors in series is programmed by select gate controlled channel hot hole and erased by channel hot electron injection along with more than 10/sup 5/ cycles of endurance and 1000 hours of data retention at 150/spl deg/C. Without an additional P-well or N-well serving as the coupling gate, the area of a bit can be as small as 8F/sup 2/, the smallest area reported for single-poly EEPROM cells.