A highly manufacturable 110 nm EDRAM process with Al/sub 2/O/sub 3/ stack MIM capacitor for cost effective high density, high speed, low voltage ASIC memory applications

A highly manufacturable 110 nm Embedded DRAM technology with stack Al/sub 2/O/sub 3/ MIM capacitor has been demonstrated successfully for the first time. High-density DRAM core with 0.1 /spl mu/m/sup 2/ cell size and high performance logic circuits have been realized at the same time by separation of the gate pattern at memory cell and peripheral logic region. Low temperature BDL process, highly reliable Al/sub 2/O/sub 3/ MIM capacitors have been developed to control process temperature. DRAM cell performance has been improved by introducing tungsten wordline, CoSi/sub 2/ plug and tungsten bitline. 7 levels Cu and CVD-OSG low-k material have been implemented to satisfy the requirement of high performance logic circuits design.