A scalar coprocessor for accelerating the G723.1 and G729A speech coders

A scalar accelerator that reduces significantly the complexity of the ITU-T G723.1 and G729A speech coders is described. Preliminary architecture space exploration indicates up to 49% reduction in the total number of instructions executed through the introduction of a few custom instructions and small changes to the reference C source code. The accelerator is designed as an autonomous unit that can be attached to a configurable RISC CPU where it makes use of the host register file and load/store pipeline.