Novel multi-layer through-die connections for package to chip power and ground connections

Novel high-density through-die connections from the front to the back of a silicon die are described. Single-diameter front-to-back through-die connections have previously been explored for various applications. The authors have explored a two-level version of multi-diameter through-die hole connections for high-density chip-to-package and on-chip power and ground distribution application. In conbast, front-side area-array chip-to-package connections, for example C4, are used for conventional power and ground distribution for high-performance microprocessor applications. Through-die power and ground distribution has the potential to save several thousand front-side power and ground chip-to-package connections in hture high- performance microprocessors by connecting power and ground primarily to backside conductor planes on the silicon die and fiom there to the package. This approach will reduce the Wiring demand on the die front-side, minimize effective on-chip inductances of nearest neighbor power/ground return paths, reduce simultaneous switching noise, and provide significant amounts of on-chip decoupling capacitance. Two-level through-die hole test structures have heen designed, fabrication processes developed and resulting interconnect structures characterized. Conductive thin-film sidewall coatings have been accomplished with conformal Tungsten and in-situ doped polysilicon CVD. New CMP based patterning has heen developed to pattem the conductive films on perforated die. A Process flow for inclusion of the through-die process into a conventional CMOS process is described. Single chip packages for die with through-die power and ground distribution architectures are proposed.