Low-Leakage micro gate valves

We have developed a device design and fabrication process for low-leakage, planar silicon gate valves. The "hole-in-the-wall" fabrication process has been used to create manually actuated gate valves that exhibit fluidic-resistance ratios greater than 27,000:1. Furthermore, theory shows that this ratio may be increased further by a factor of five because the current valve seat has not been optimized. The fabrication process makes possible, for the very first time, planar micro valves with valve seats that completely encompass the fluid flow. As opposed to previously published planar micro valves, there is no direct leakage path around the valve gate because this new fabrication approach places a flow orifice in the center of the wall of a channel. With the channel walls used as a valve seat, the location of this orifice reduces the leakage above and below the gate, a problem inherent in all planar micro-fluidic valves. Our robust, wafer-level, three-mask, self-aligned process is described and includes important details regarding smoothing of the valve-seat surface.