A high speed dual modulus divider in SOI CMOS with stacked current steering phase selection architecture

This work describes a high frequency dual modulus divider designed and fabricated in a 0.35 /spl mu/m PDSOI process, employing a stacked topology phase switching scheme. SOI CMOS technology is exploited to allow current re-use in a higher supply voltage than dictated by single device breakdown. Measurements show the circuit operating at 3GHz (Vdd = 6.8V.).