Voltage optimization for state of the art RF-LDMOS for 2.1 GHz W-CDMA cellular infrastructure applications

The breakdown and operating voltage optimization of a RF-LDMOS power amplifier (PA) transistor for high power base station applications is presented. For a given device a local maximum in linear PAE is observed to be a function of the drain supply voltage. Best results were achieved for an optimized 10 mm device with a supply voltage of 32V. W-CDMA results (single carrier W-CDMA 3GPP signal at 2.14GHz, 8.5dB P/A) were 29% PAE with Pout=162mW/mm at -45dBc ACP, and 62% PAE with Pout=785mW/mm at P3dB with tuning for optimum back-off performance. To our knowledge these results represent the highest PAE's for this back-off level ever reported for transistors of any material that are appropriate for high power infrastructure applications, as well as state of the art peak power densities for silicon.