A new synchronous mirror delay with an auto-skew-generation circuit

A new synchronous mirror delay with an auto-skew-generation circuit is proposed to automatically detect clock skew and generate internal clock to synchronize the internal clock to the external clock within 4 clock cycles even though it has no replica delay. Having no replica delay enables this circuit to be transplanted into various products without any addition or subtraction of any circuits no matter how much the. clock skew is as long as the process technology is the same. That helps the circuit designer think little of the many problems caused by delay difference between original delay and replica delay. HSPICE simulation results show that this circuit detects clock skews (2.7 ns /spl sim/ 3.7 ns) using clock frequencies (80 MHz /spl sim/ 285 MHz) and eliminates clock skew within 4 clock cycles.