Automatic analog layout retargeting for new processes and device sizes

This paper presents an automatic analog layout resizing tool that can generate a new layout incorporating the target technology process and the target transistor sizes. The tool automatically preserves the analog layout integrity by extracting layout symmetry and matching, and then solving the constrained layout generation problem using a combined linear programming and graph-theoretic approach. The tool has been applied successfully to integrate specified transistor sizes and to migrate layouts for various analog designs from TSMC 0.25 /spl mu/m CMOS to TSMC 0.18 /spl mu/m CMOS process with comparable performances to re-design.