Design and implementation of a reconfigurable FIR filter

Finite impulse response (FIR) filters are very important blocks in digital communication systems. Many efforts have been made to improve the filter performance, e.g., less hardware and higher speed. In addition, software radio has recently gained much attention due to the need for integrated and reconfigurable communication systems. To this end, reconfigurability has become an important issue for the future filter design. In this paper, we present a digit-reconfigurable FIR filter architecture with the finest granularity. The proposed architecture is implemented in a single-poly quadruple-metal 0.35-/spl mu/m CMOS technology. Measurement results show that the fabricated chip consumes 16.5 mW of power when operating at 86 MHz under 2.5 V.