Improved current-source sizing for high-speed high-accuracy current steering D/A converters

This paper describes a design methodology for the basic current source cell circuit of high-speed high-accuracy current steering D/A converters taking into account mismatching in all the transistors of the cell. Previous works consider arbitrary safety margins in the sizing process. The presented approach allows a more accurate selection of the optimal design point. The design methodology is illustrated for a particular design of a 0.35 /spl mu/m CMOS 12 bit 400 MHz current-steering segmented D/A converter.