A 1.6 GHz downconversion sampling mixer in CMOS

This paper describes a downconversion sampling mixer design in CMOS. A MOS switch linearization technique is utilized, which enables high frequency sampling of an RF signal. The measurement results show a 1.6 GHz input signal downconversion with a sampling rate of 1.55 GHz, +22 dBm IIP/sub 3/, 1.4 ps sampling jitter, 8 dB conversion loss and 25 dB noise figure. The chip is fabricated in a 0.35 /spl mu/m 3.3 V CMOS process and bonded directly onto a printed circuit board. The downconversion sampling mixer occupies an active area of 0.05 mm/sup 2/ and consumes 43 mW power.