Low-power CMOS PLL for clock generator

This paper presents a design of phase-locked loop suitable for the clock generation of DSP applications. The challenge of a low-jitter PLL is observed in the design tradeoff between noise contributions and bandwidth choice. An extra logic scheme with a PFD (phase/frequency detector) is applied in the lock detection. For power noise at low and high frequencies, the proposed VCO is proven by analysis and simulation. The supply sensitivity of the measured VCO is less than 0.5%/V over a large operation range. The measured loop bandwidth is 325 kHz, and the rms value of long-term jitter is 40 ps. The power consumption of the PLL core is 5.5 mW at 2.5 V. The overall circuit is implemented in a 0.35 /spl mu/m 1P4M standard CMOS process with a supply range of 1.3 to 3.3 V and the occupied area of the proposed PLL is 460/spl times/560 /spl mu/m/sup 2/.