A high speed low input current low voltage CMOS current comparator

A new high speed low input current comparator is proposed in this paper. Based on a simple negative feedback scheme around the transimpedance stage, with an emphasis on a very large loop-gain, the transformed voltage signal is maintained at the lowest swing that results in a speed improvement. On a 0.25 /spl mu/m TSMC CMOS process, simulation results demonstrate propagation delays of. 3.6 ns with /spl plusmn/100 nA input current and 1.5 Volts power supply, while the smallest input current is /spl plusmn/50 pA. Performances are also shown with other V/sub DD/ such as 1.0 and 1.8 Volts.