A compact phase interpolator for 3.125G Serdes application

This paper describes an area-efficient, low-voltage, low-power phase interpolator for clock recovery in a 3.125/2.5 Gbps dual mode serial link application. It has been implemented in both 0.15 /spl mu/m and 0.13 /spl mu/m digital CMOS processes. It occupies 0.02 mm/sup 2/ and dissipates less than 10 mW in both processes. The measurement results from the 0.13 /spl mu/m transceiver show a BER<10/sup -14/ with the presence of /spl plusmn/200 ppm frequency offset and 0.65 UI/sub p-p/ combined deterministic, random and sinusoidal jitter.