Experimental characterization of a self-calibrating delay-locked delay-line

The results arising from the experimental characterization of an on-chip all-digital non-linearity calibration technique for digitally controllable delay-locked delay-lines (DLLs) are presented in this work. A 32-tap DLL in which the delay introduced by each delay element can individually be controlled by means of a digital control word has been designed, fabricated using a 0.6 /spl mu/m 3-metal CMOS process and extensively tested. The delay-line is provided with an all-digital calibration circuit that is able to correct the non-linearity of each cell with an iterative algorithm. The non-linearity of each cell is first measured by means of a statistical test and then properly corrected. The experimental results completely match with theory and simulations, showing outstanding maximum non-linearities very close to /spl plusmn/1% after the calibration. "Almost ideal" DLLs are thus obtained.