Addressing a high-speed D/A converter design for mixed-mode VLSI systems

This paper describes a high-speed D/A converter design for mixed-mode systems. Capacitive coupling induced by inter-chip interconnects should be considered for mixed-mode systems, and on-chip interconnects should be treated as transmission lines in the circuit simulation as operating speed reaches the GHz range. A robust FIFO built in the D/A converter can absorb data-dependent input timing variance, the worst-case margin of which is /spl plusmn/1.5/spl times/T/sub CLK/. Distributed LCR transmission line models for on-chip interconnects produce more accurate simulation results at 1 GHz clock frequency than lumped models. Measurement results verify the accuracy of the interconnect models. Behavioral modeling methodology is also presented in this paper for optimized D/A converter design.