High speed memory subsystem for the SIMD/MISD class of advanced embedded computing

The enhanced high speed RAM is designed for the experimental SIMD/MISD class of computer. The computer is configurable in any of the two said classes. In the total experimental SIMD/MISD class computer, IBM PC will act as a front end system. The RAM becomes a part of the back end system. This paper outlines the design strategy and implementation techniques required for implementing the RAM subsystem.