Timing jitter in a 1.35-GHz single-ended ring oscillator

In this paper, we have simulated the timing jitter due to device noise in a three stage single-ended ring oscillator, and a methodology to efficiently simulate timing jitter has been developed. Simulation result shows the variation of absolute jitter due to flicker noise has t dependence, while for white noise, it is t/sup 0.5/ dependence, which are consistent with accepted theory. Two important parameters cycle jitter, and cycle to cycle jitter used to describe jitter performance can be obtained from simulation. The methodology described in this paper is also applicable to other types of oscillators such as differential ring oscillators and LC oscillators, as well as other kinds of noise sources as power supply and substrate noise.