Signal integrity improvement in the TMDS link at UXGA

Transition Minimized Differential Signaling (TMDS) link connecting a Digital Visual Interface (DVI) compliant Transmitter and Receiver between a PC and a Display Device was characterized at 162MHz, that is the UXGA pixel clock frequency. The transmission line model of the link was simulated using Pspice and it was observed from the simulation data as well as the data collected from bench that a matching source termination at the transmitter end in addition to the far end termination at the receiver improved the signal integrity. The improvements were seen in the eye at the receiver with considerable reduction in data dependent jitter. Currently the DVI Revision 1.0 does not specify the requirement of a source termination.