Control versus compute power within a LEDR-style self-timed multiplier with bypass path

The design of a self-timed multiplier using Level-Encoded Dual Rail IO is presented. A concern with LEDR compute blocks is the ratio of the power consumed by the control logic used for dual rail IO signal decoding/encoding and arrival detection versus the power needed for the actual computation. Boolean multipliers using a CSA architecture of sizes 8/spl times/8=16 and 16/spl times/16=32 are implemented via a 0.5u standard cell library. Post-layout transistor level simulations indicate a compute to control ratio of 1.2 for the 8/spl times/8 multiplier, and 2.5 for the 16/spl times/16 multiplier. These ratios are improved to 3.4 and 8.3 respectively via alternate versions of the multipliers that use bundled data signaling to reduce control power. The multiplier design includes a bypass path that allows the combinational delay of the multiplier to be skipped if the multiplier result is not required.