A low-power 2.1 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic

A high-speed, low-power 32-bit carry lookahead adder is presented. We have developed Dual Path All-N-Logic (DPANL) and applied to 32-bit adder design for higher performance. The speed enhancement is mainly due to reduced capacitance at each evaluation node of dynamic circuits. This adder can operate at frequencies up to 2.1GHz for 0.35um 1P4M CMOS technology and is 31.3% and 27.3% faster than the adders using All-N-Transistor (ANT) and All-N-Logic (ANL), respectively. It also consumes 29.2% and 15.4% less power than the ANT adder and ANL adder, respectively.