VLSI design and implementation of high-speed Viterbi decoder

This paper presents a new architecture for high-speed Viterbi decoder with low power dissipation based on the modified T-algorithm and modified trace-back methods. The former algorithm is used to reduce the unnecessary operations in path metric computation, while the latter is adopted to reuse the already generated trace-back routes to reduce the times of trace-back operations, so the power consumption can be saved. High throughput and short decoding latency are achieved by parallel computation in the add-compare-select unit and pipeline structure in the survivor-memory-unit. The complexity of the (2,1,7) Viterbi decoder is about 50,000 gates with a decoding latency of 32 clock cycles, and an area of 3.88 mm/sup 2/ including IO pad with a throughput of 200 Mb/s using 0.25 /spl mu/m technology.