An interleaved round-robin scheduling chip for 1.2 G-bps ATM networking

This paper proposes an interleaved round-robin (IRR) scheduling chip for providing good cell-delay-variation (CDV) performance in ATM networking. The chip is designed to carry out a multi-class IRR scheduling algorithm to support 256 connections with 8 classes concurrently. The multi-class method reduces its sorting complexity from 256 to 8. The chip has been fabricated by the TSMC 0.6-/spl mu/m SPDM process. Its core size is 3.5/spl times/3.5 mm/sup 2/ and power dissipation is 176-mW at 33 MHz. It is able to support a 1.2 Gbps ATM network.