Digital matched filter ASIC

The architecture of a digital matched filter (DMF) and the selected technology used is described. The characteristics of the DMF ASIC are summarized in tabular form. Three architectures are considered for the implementation of a DMF ASIC. First, there is the conventional trapped delay line architecture which requires a large adder tree. The second architecture is the systolic array DMF which consists of a number of identical stages cascaded together. The third architecture is the bank-of-correlators DMF, in which the reference code is recirculated around through the delay line. Since the objective is to maximize the length of the DMF, the tapped delay line architecture is selected. The tapped delay form is designed to support BPSK, QPSK, and OQPSK chip modulation. Matched filter lengths of up to 256 chips can be supported by cascading 4 ASICs. The DMF is designed as a gate array using an advanced double metal, 1.5 mu m CMOS process. The regularity of FIR filter architecture allows the core of the device to be laid out very compactly resulting in efficient usage of the gate array.<>