Voice excited predictive coder (VEPC) implementation on 10 MIPS signal processor

In this paper, we discuss the Implementation of a low bit-rate linear prediction base-band coder on a bipolar signal processor having a processing capacity of 10 millions of instructions per second (MIPS). We show that the implementation of our algorithm requires less than 5 MIPS, with a ROS occupancy less than 5 K instructions. Some quality evaluation tests are also reported, and show that this type of coder operating at 7.2 kbps, provides a good communications quality, an intelligibility which is sufficient for most of telephony applications, and a perfect speaker recognition (natural voice).