High speed signal processing, pipelining, and VLSI

In this paper we discuss issues arising in the design of highly pipelined VLSI circuits for high-speed signal processing applications. Problems such as clock skew, buffer design, clock distribution network, and timing simulation are addressed, and methods of alleviating them are presented. The impact of technology on the degree of pipelining is discussed. Some design examples, including an 8-bit systolic multiplier fabricated in 2.5 micron CMOS technology and tested up to 70 MHz multiplication rate, are presented. The extension of this design to a systolic multiply-add/accumulate chip and its applications are briefly discussed.