On the difficulties of utilizing current technologies to perform 100MHz DSP

This paper is an extension of work first reported at ICASSP '85 in Tampa. In that conference this author reported on a 50 MHz real-time digital adaptive FIR filter using 16-bit, fixed-point arithmetic. This processor is a massively parallel architecture and was designed using the latest generation CMOS technologies. The first unit is now complete and in service. This paper will summarize the final results of this research project and then extend this discussion to elaborate on the potential problems that may arise when we push this architecture to meet 100 MHz real time digital signal processing (DSP*) requirements and beyond.