A practical study on the architecture of VLSI DSP

This paper describes some results of analysis on an architecture focusing on the pipeline structure of multiplier. Throughput of a 16 bit multiplier with fixed point arithmetic was analyzed for a single cycle structure, a 2-stage pipeline structure and a 3-stage pipeline structure. Total efficiency which includes overheads inherent to a pipeline structure was examined for each structure based on the programs made for practical use such as a 32 kb/s ADPCM codec, echo canceler, 19 section filter banks for voice recognition etc. Each analysis showed that the 2-stage pipeline structure is a suitable choice from the view points of efficiency and simplicity of programming.