Systolic architectures based on barrel shifters for real-time signal and image processing

The throughput in real-time digital signal processing (DSP) applications is limited by both the capability of the processors employed for number-crunching operations and the capacity of a supporting communications link. The systolic architectures eliminate the memory bandwidth problems by allowing multiple computations for each memory access and hence makes possible a high throughput in real-time applications. In conventional systolic arrays, the computational element includes a multiplier and an accumulator (MAC). The multiplier in the basic cell requires either large chip area if high speed is desired or time consuming if serial architecture is used. The replacement of the multiplier by the barrel shifter has been proposed in this paper. The new basic cell consists of a barrel shifter and an accumulator (BSAC). By the variations of the connection among the basic cells, the throughput data rate can be increased significantly. Also, a large reduction in the number of the gates can be achieved. The results obtained indicate that the BSAC-based systolic arrays can outperform the conventional ones and achieve throughput data rate of the order of 100 MHz or higher.