Scheduling and simulation of neural nets on a DSP accelerator

A description is given of the Software Development System (SDS), which consists of a preprocessor and a general-purpose scheduler, and which has been used to generate schedules for two-layer fully connected neural networks. The particular structure (precedence graph) of the code of the back-propagation algorithm which is used to generate parallel code is described. Also described is the prototype ADSP-2100 parallel processing system that has been built and on which some of the smaller size neural networks have been implemented. Cycle count for scheduling the back-propagation algorithm on various sizes of neural networks and two digital signal processing (DSP) architectures and associated throughput rates obtained are given. Cycle counts for computation (with concurrent data communication) and communication only are also obtained.<>