Characterizing dynamic and leakage power behavior in flip-flops

This paper presents a detailed analysis of power consumption in a variety of flip-flop designs including scannable latches. The analysis was performed by implementing and simulating the different designs using 70 nm, 1 V CMOS technology. First, we perform a detailed characterization of the dynamic power consumption due to output transitions, and that due to clock and data transitions when there is no output transition. Further, we also characterize the leakage behavior of each of the flip-flop designs and specifically, characterize the input dependence of leakage.