25ns 256K × 1/64K × 4 CMOS SRAMs

DEMANDS FOR FAST ACCESS TIMES as well as low power dissipation have been increasing, even in high density static RAMS. This paper will describe 256K CMOS static RAMS (nibble wide and bit wide), that utilize short bit line and a Schmitt trigger data bus latch circuit architecture. Either a bit wide organization or a nibble wide organization is obtained by alternating the aluminum layer mask. A typical address access time of 25ns and an active power dissipation of 45mW (x4) / 30mW (xl) at 1MHz have been achieved.