A submicron VLSI memory with a 4b-at-a-time built-in ECC circuit

THIS PAPER WILL REPORT ON AN experimental 1Mb dynamic memory, utilizing a 4 bit-at-a-time Error Checking and Correcting (ECC) circuit, and a high-sensitivity distributed sense circuit. A 1Mb DRAM using a 20μ^2 cell was designed and fabricated with an 0.8~ CMOS process