Design and technology for DMOS E/D logic

DMOS IIAVE FOUND a promising field of application in enhancement-depletion (E/D) logic 1,2. As a matter of fact, besides their short-channel and high voltage features, they allow the direct integration of enhancement drivers together with depletion loads without any supplementary step; Figure 1. Making use of standard technological tools, the DMOS technique may be considered as an easy way to improve actual MOS performance without depending on more sophisticated tcchnologics3. Howewer, for a practical implementation, problems arise in two fields, which prompted this study.