A 32 x 9 ECL dual address register using an interleaving cell technique

A 32-WORD BY 9-BIT Dual Address Register Stack (DAS) which uses an interleaving ECL cell technique to achieve address access speeds comparable to previously-reported speeds for single port ECL memories' will be described. The ECL LSI device has two independent memory ports, each having full data, read/write capability, parity function and-output storage register. In addition, as shown in the functional block diagram, Figure 1, an error circuit signals when operations defined as system errors; e.g., simultaneous write to the same address, are performed.