Testability considerations in the design of the MC68340 Integrated Processor Unit

An application-oriented discussion of the design-for-test techniques utilized on the MC68340 Integrated Processor Unit is presented. The principal topics covered are the MC68340 test methodology, structured design techniques, and the use of CAD (computer-aided-design) tools for automatic test pattern generation. Incorporation of structured design techniques for the modules made it possible to obtain higher fault coverage with automatic test generation. The test logic overhead attributed to the scan path design in the peripheral modules varied greatly. The area overhead ranged from 12% for random logic; sections to 50% for a regular register file section. Timing paths caused by the scan path design, were identified and corrected by circuit simulation. Potential problems, such as asynchonous resets, clock cones, and IMB (internal-intermodule-bus) signals, were handled on an individual basis by utilizing the constrained-inputs test generation scheme. A high degree of modularity/portability was maintained for the test patterns.<>