A SEM-E module avionics computer with PI-Bus backplane communication

The author describes the system architecture of a MIL-STD-1750A-based mission processor utilizing dual VHSIC Phase 2 TM-Bus and dual VHSIC Phase 2 PI-Bus for intermodule level communication. The mission processor consists of 18 surface-mount SEM-E modules and five high-density power supplies mating with an 18 layer G-10 backplane in an air-cooled chassis. The system-level interfaces consists of a dual PI-Bus for intermodule communication, a dual TM-Bus for intermodule operational test and maintenance, an IEEE-488 interface to an external software development platform, two differential small computer system interface (SCSI) buses, three dual redundant MIL-STD-1553B serial communication buses, and several digital and analog discrete I/Os. The author presents a comparison of the defined cycle sequence of each of the basic PI-Bus messages to the observed cycle structure of these message types in the system. The impact of chaining a sequence of PI-Bus messages is examined. Data on the impact of PI-Bus traffic on module performance under various conditions are examined.<>